When realizing memory circuits, a basic distinction is drawn on the basis of the storage architecture; the most common representatives are referred to as the NAND and NOR architectures. In both architectures, one-transistor memory cells are arranged in matrix form and are driven via signal connections referred to as word and bit lines.
Whereas in NAND architectures a multiplicity of switching elements or storage elements are connected in series with one another and are driven via a common selection gate or a selection transistor, the respective switching elements in NOR architectures are organized in parallel or in matrix form, as a result of which each switching element can be selected individually.
FIG. 1 shows a simplified illustration of a so-called SNOR architecture (selective NOR), in which, in contrast to the NOR architecture with “common source” structure, the individual switching elements SE1, SE2, . . . are driven selectively via a respective source line SL1, SL2, . . . and via a respective drain line DL1, DL2, . . . This selective driving is carried out for example by means of respective bit line controllers BLC which, as it were, realize the common bit lines BL1, BL2, . . . Further shrinks or more extensive integration of semiconductor circuit arrangements can be carried out in this way, since the SNOR architecture does not rely on a predetermined minimum cell transistor length or channel length.
FIG. 2 shows a simplified illustration of a conventional layout of the SNOR architecture in accordance with FIG. 1. In accordance with FIG. 2, the switching elements or memory elements SE1, SE2, . . . are formed in active areas AA of a semiconductor substrate which have a substantially straight strip-type structure. On the multiplicity of strip-type active areas AA arranged in columns there overlie, in rows, layer stacks or word line stacks WL1, WL2, . . . likewise formed in strip form. Each crossover point or overlap region between such a strip-type active area AA and a word line stack WL1 to WL3 formed in strip form thus represents a multiplicity of switching elements or memory elements SE.
Contacts are necessary for making contact with respective drain regions D and source regions S, which contacts are usually formed in the active areas AA, but may often also extend into an adjoining isolation region STI (Shallow Trench Isolation). In a further layer lying above that, which preferably represents a first metallization layer, there are then situated the source lines SL1, SL2, . . . and also the drain lines DL1, DL2, . . . for the respective bit lines BL. In this case, the drain lines are connected to the associated drain regions D of the active area AA via corresponding contacts K, the source lines being connected to the associated source regions S via corresponding contacts in the same way.
What is disadvantageous, however, in the case of such a conventional bit line structure is that a more than twice as intensive metallization is present on account of the additional source lines in comparison with a common source architecture, which represents a limiting factor for more extensive integration or further shrinks.
Therefore, to improve an integration density, it is proposed, in accordance with document DE 100 62 245 A1, to form the source lines and drain lines as spacers at an insulating web and to allow contact to be made with the associated source regions and drain regions via an additional insulation layer with suitable openings. Furthermore, however, the space required on account of the source lines and drain lines formed at the substrate surface and lying parallel is relatively large and prevents more intensive integration.
Furthermore, document U.S. Pat. No. 6,008,522 has disclosed a buried bit line which is formed in an insulation trench and in each case makes symmetrical contact with source regions and drain regions via a terminal layer.
Accordingly, a bit line structure and an associated fabrication method is needed, which, in particular with SNOR architectures, allows further integration to be realized with a reduced need for space.